EVAL-AD1896EB【PDF 3/28 页】Automotive Low-Cost Non-Volatile FPGA Fa

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Sheet目录362799

1页 2页 [3页]4页 5页 6页 7页

REV. 0

–3–

EVAL-AD1896EB

MUTE_IN

RESET

SMODE_IN_2

SMODE_IN_1

SMODE_IN_0

BYPASS

DGND

GRPDLYS

MCLK_I

MCLK_O

SDATA_I

VDD_IO

LRCLK_I

SCLK_I

JP4 CRYSTAL OSC./EXTERNAL CLK

DDI-HDR3, SPDIF-J1,

TOSLINK-U4

S3 (8-POSITION SWITCH)

AD1896

MUTE_OUT

WLNGTH_OUT_1

WLNGTH_OUT_0

SMODE_OUT_1

SMODE_OUT_0

TDM_IN

DGND

MMODE_2

MMODE_1

MMODE_0

SCLK_O

VDD_CORE

SDATA_O

LRCLK_O

S4 (8-POSITION SWITCH)

DDO-HDR5, SPDIF-J2,

TDM_OUT-HDR2

TDM IN HEADER HDR1

JP1 (4-POSITION JUMPER)

Figure 1. Key Jumpers and Switches on the Evaluation Board

Table I. Pinout Table for 10-Pin Header Connectors

HDR1 (TDM_IN)

HDR2 (TDM_OUT)

HDR3 (DDI)

HDR5 (DDO)

2, 4, 6, 8, 10

5 V (O)

TDM_I (I)

SCLK_O (I/O)

LRCLK_O (I/O)

GND

5 V (O)

SDATA_O (O)

SCLK_O (I/O)

LRCLK_O (I/O)

GND

5 V (O)

SDATA_I (I)

LRCLK_I (I/O)

SCLK_I (I/O)

GND

5 V (O)

SDATA_O (O)

SCLK_O (I/O)

LRCLK_O (I/O)

GND

DIGITAL AUDIO INPUT SIGNALS

Input serial port of the AD1896 can be driven in various ways

using this evaluation board.

1. RCA phone jack (J1) or TOSLINK (U4) optical connector

can be used to input the AES/EBU or SPDIF signal to the

SPDIF receiver CS8414 (U1). SPDIF receiver generated

SCLK_I, LRCLK_I, and SDATA_I signals drive the input

serial port of the AD1896.

SPDIF input is supported only

when the AD1896 serial input port is in SLAVE mode (Switch

S4 position 3 to 7) and supports all input serial data formats

except R

-24 bit and R

-20 bit (Switch S3 positions 2,

3). The

SPDIF receiver limits input sample rates to 96 kHz.

2. Alternatively, an external data header (HDR3) can be used

to directly source all three signals SCLK_I, LRCLK_I, and

SDATA_I from an external source. Unlike SPDIF receiver,

Table II. Input and Output Serial Port Modes

MMODE_[2:0]

S4 Switch Position

Master/Slave Modes

Both Serial Ports are in Slave Mode

Output Serial Port is Master with 768 f

S_OUT

Output Serial Port is Master with 512 f

S_OUT

Output Serial Port is Master with 256 f

S_OUT

Matched Phase Mode

Input Serial Port is Master with 768 f

S_IN

Input Serial Port is Master with 512 f

S_IN

*Input Serial Port is Master with 256 f

_IN

In MASTER MODE operation, maximum sample rate for Master Port is limited to 96 kHz.

input sample rate up to 192 kHz is possible (input port in

slave mode) and set by an external source. All input serial

data formats and master/slave clock modes are supported.

SCLK_I and LRCLK_I signals of the input serial port are

bidirectional signals. Logic levels on pins MMODE_ [2:0]

control the direction of these signals. When the input serial port

is in master mode, these signals are generated by the AD1896;

whereas, in the slave mode these signals are provided by an

external source. MMODE_[2:0] pins are set by the 8-position

Switch S4. Tables II and III show the master/slave clock mode

corresponding to each switch position.

Input data format, such as, I

S, LJ, or RJ is set by the logic

levels on SMODE_IN_[2:0] pins as shown in Table IV. Set the

8-position Switch S3 on the evaluation board for the proper

input data format.

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